`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    10:50:10 11/03/2014 
// Design Name: 
// Module Name:    Output_2_Disp 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module 	 Prep_IO(input  wire clk_100mhz,
	// I/O:
						input  wire[15:0]SW,
						output wire led_clk,
						output wire led_clrn,
						output wire led_sout,
						output wire LED_PEN,
				
						output wire seg_clk,
						output wire seg_clrn,
						output wire seg_sout,
						output wire SEG_PEN
						);
					
    wire[31:0]Div;
    wire [15:0]led_data;
	//wire [31:0]display;
	wire [63:0]disp_data;
	wire [15:0]ioOut;
	
    //seg7 seg7_p(ioOut,display);
    
    clk_div       U8(clk_100mhz,1'b0,Div);
    
	P2S 			  #(.DATA_BITS(64),.DATA_COUNT_BITS(6)) 
						  P7SEG (clk_100mhz,
									1'b0,
									Div[24],
									disp_data,
									seg_clk,
									seg_clrn,
									seg_sout,
									SEG_PEN
									);
										
	LED_P2S 			  #(.DATA_BITS(16),.DATA_COUNT_BITS(4)) 
					      PLED (clk_100mhz,
									1'b0,
									Div[24],
									led_data,
									led_clk,
									led_clrn,
									led_sout,
									LED_PEN
									);
 
    SOC                     soc0(
                                Div[24],
                                SW[0],
                                SW[14],
                                SW[10:1],
                                ioOut
                                );

assign led_data=~{ioOut[0],ioOut[1],ioOut[2],ioOut[3],ioOut[4],ioOut[5],ioOut[6],ioOut[7],ioOut[8],ioOut[9],ioOut[10],ioOut[11],ioOut[12],ioOut[13],ioOut[14],ioOut[15]};					//led灯作为交通灯
assign disp_data = {ioOut[7:0],ioOut[7:0],ioOut[7:0],ioOut[7:0],ioOut[7:0],ioOut[7:0],ioOut[7:0],ioOut[7:0]};

endmodule





		


